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Model 74851 4-Ch 500 MHz A/D with DDC & 4-Ch 800 MHz D/A with DUC, Kintex UltraScale -6UcPCI

This product is in the Inactive Life Cycle. Please contact Pentek for additional information.

Block Diagram




Life Cycle Management

Ordering & Warranty


Free Lifetime Support

  • Complete radar and software radio interface solution
  • Supports Xilinx Kintex Ultrascale FPGAs
  • Supports VITA-49.2 VITA Radio Transport standard
  • Four 500 MHz 12-bit A/Ds
  • Four multiband DDCs (digital downconverters)
  • Two DUC (digital upconverter)
  • Four 800 MHz 16-bit D/As
  • 10 GB of DDR4 SDRAM
  • Sample clock synchronization to an external system reference
  • LVPECL clock/sync bus for multimodule synchronization
  • Optional LVDS and gigabit serial connections to the Kintex Ultrascale FPGA for custom I/O
  • Optional 400 MHz 14-bit A/Ds
  • Ruggedized version available


Model 74851

Jade Xilinx Kintex UltraScale FPGA Family Brochure
Jade Xilinx UltraScale

Model 74851 Block Diagram

Please refer to the product datasheet for a larger version of the block diagram

Hardware and Software Manuals - ( top )

Please note that some hardware and software manuals are used for more than one Pentek product. Although the model numbers given in the description of each manual below may vary, these manuals are all used for the product described on this web page.

A complete set of user manuals is provided in HTML format. Access to detailed documentation of the IP Core modules and their programmable registers is only available in the HTML version of the operating manual. Instructions for getting the HTML version of the user manuals is provided in the User Manual Library document listed below.

Part No.
800.48145 User's Guide Navigator BSP for Jade User's Guide - Windows & Linux 4.2 (9/29/2023)
800.71851 Operating Manual 2- Chan 500 MHz A/D, 2- Chan 800 MHz D/A with DDCs, DUC Jade XMC Module 1.3 (5/1/2018)
822.71851 Release Note Model 71851 FDK Revision Histories 5.0 (6/16/2023)

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