| Home > Pipeline Vol. 16 No. 1 > XMC: A Mezzanine for all Seasons |
Mezzanine cards have played an essential role in real-time embedded systems since the earliest days of single board computers and standard backplanes. They offer a wealth of specialized signal interfaces, data converters, connectors, and transceivers along with dedicated engines for protocols, networks and signal processing. Standardization of the mechanical and electrical characteristics of these mezzanine cards enables system integrators to deliver specialized, high-performance embedded applications by judiciously combining open-architecture I/O products with processor boards.
Making its debut in 1994 as IEEE standard P1386.1, the PMC (PCI mezzanine card) was successfully adopted for both commercial and government electronic systems. Based on the mechanical specifications for the P1386 CMC (common mezzanine card), it included three 64-pin connectors to support a PCI bus interconnect to the carrier board, as well as a fourth 64-pin connector for user I/O.
During the next decade, important extensions to the PMC standard included conduction-cooled versions for severe environments, pin definitions for P4 I/O, and the adoption of the Processor PMC (PrPMC) specification.
When a proposal for standardizing gigabit serial switched fabrics shook the embedded computing community in 2002 as part of the VME Renaissance, a natural extension of that technology to PMC modules was inevitable. Defined under VITA 42, the XMC specification extends the PMC card by adding new connectors to support gigabit serial interfaces plus a growing list of alternative I/O standards.
The hallmark of any successful standard is that it continues to evolve with technology, and none offers a better example than XMC. Figure 1 shows the current listing and status of the many standards defining XMC under VITA 42.
VITA 42.0 is the base specification that includes general information, reference and inheritance documentation, dimensional specifications, connectors, pin numbering and primary allocation of pairing and grouping of pin functions. This document is still designated as a draft document, but it was released for trial use for an 18-month period ending March 2007. Recommendations gathered during the trial will be used to produce a final released specification.
XMCs can be single- or double-wide modules that use a pin-socket connector with 114 pins arranged in a 6 x 19 array. A single width XMC can have one or two connectors with pin functions as shown in Figure 2. A double width XMC can have up to four connectors.
To support gigabit serial interfaces, notice that both P15 and P16 connectors define 10 full-duplex differential pair lines. The VITA 42.0 base specification does not dictate signal types, data rates, protocols, voltage levels or grouping for these signals. Instead, it wisely leaves that up to the several sub-specifications that follow, allowing XMCs to evolve as new standards emerge.
In fact, contrary to the fundamental mission of supporting serial interfaces, the first sub-specification, VITA 42.1, defines these same pins for Parallel RapidIO. While VITA 42.1 is approved and fielded, few vendors have embraced this standard and have instead opted for the more popular serial protocols.
VITA 42.2, 42.3 and 42.4 define true serial switch fabric protocols for Serial RapidIO, PCI Express and Hypertransport, respectively. The first two are already approved and beginning to appear as mainstream choices for a widening range of board and silicon vendors.
In fact, two major silicon vendors have announced new processors well-suited for embedded computing applications that incorporate serial interfaces and protocol engines right on the chip. Texas Instruments offers the TMS320C6455 DSP processor with Serial RapidIO, while the Freescale MPC8641 includes both PCI Express and Serial RapidIO interfaces. These native interfaces simplify carrier board design and significantly boost peripheral I/O transfer rates by taking advantage of XMC modules.
VITA 42.5 defines the popular Xilinx Aurora protocol for use in XMC. This lightweight link layer protocol is quite attractive for XMC modules because many XMCs only need to move data from a dedicated source (like an A/D converter) to a dedicated destination (like memory on a processor board). The extra protocol layers necessary to support a full switched network and routing can significantly reduce the payload data rate and add complexity and cost at both ends of the link. This standard is still in the definition phase.
As shown in Figure 2, most of the pins on P15 are reserved for serial links, power and other functions, but P16 has a wealth of user-defined pins now being addressed by the VITA 42.10 General Purpose I/O draft specification. It offers a standardized way of implementing interfaces for popular system I/O including Ethernet, USB ports, RS-232, RS-485, Serial ATA, Fibre Channel, and SAS (Serial Attached SCSI). The clear benefit here is that by following these definitions, XMC and carrier board designers can achieve a much wider range of inter-operability, the essential goal of industry standards.
In recent years, FPGAs (field programmable gate arrays) have permeated mezzanine card architectures for reasons entirely incidental to XMC, and yet today FPGAs represent the single most significant catalyst for XMC adoption.
FPGAs offer a collection of resources ideally suited for peripheral I/O functions. FPGAs may be configured to implement numerous electrical interface standards as well as a variety of protocol engines. By reconfiguring its FPGA, not only can a single I/O product replace several legacy products, it can also adapt to future standards and protocols as well. This forestalls product obsolescence, both at the board level and at the deployed system level.
Another reason FPGAs find their way onto mezzanine cards is their unmatched ability to implement real-time signal processing and high-level local control. FPGAs deal effectively with the very high frontend data rates for A/D and D/A converters, network interfaces, sensor arrays and high-speed data channels by mustering a troop of high-performance hardware resources, configured to match the specific task at hand. For more sophisticated front-end processing, most FPGAs now feature DSP engines with built-in hardware multipliers to tackle the toughest algorithms with ease. Arrays of these engines can be deployed in parallel, completely surpassing the capabilities of general-purpose programmable RISC or DSP processors that must execute serial instructions.
By performing these types of intensive protocol, formatting, decoding and DSP functions on the mezzanine, the workload for the processor on the carrier board can be significantly reduced. This may lead to fewer processors or fewer processor boards in the system, for considerable savings in system cost and size.
With integrated microcontrollers, FPGAs can now implement a complete system-on-a-chip. Executing a program coded into the FPGA or from an external FLASH, these microcontrollers can perform complex processing tasks to implement real-time control functions for adaptive processing, signal classification, target identification and object recognition. Having intimate contact with the surrounding DSP hardware, FPGA microcontrollers can modify real-time operating parameters and modes very efficiently—often well beyond the scope of larger systems with more loosely coupled elements.
With such widespread use of FPGAs on mezzanines, the emergence of built-in gigabit serial interfaces on these devices was a major windfall for XMC. During the last five years, both Xilinx and Altera have invested heavily in developing this technology, and have now produced three generations of FPGAs with gigabit serial interfaces as shown in Figure 3.
Xilinx offers their RocketIO GTP transceivers on the latest Virtex-5 LXT family devices with bit rates up to 3.125 GHz. Altera offers their Stratix-II GX multigigabit transceivers with bit rates up to 6.375 GHz. Both vendors support these physical interfaces with SERDES (serializer/deserializer) hardware engines that perform serial/parallel conversion so that data and clock are combined in the signaling on each differential pair over the external serial channel.
Protocol engines for specific standards can be configured using FPGA logic so that FPGAs can adapt to different protocols as required. They interface to the SERDES and correctly process protocol-specific packets, header information, control functions, error detection and correction, and payload data format. The strategy makes FPGA-based XMC modules truly "fabric agnostic" and allows one hardware design to be deployed in several different fabric environments.
The new Xilinx Virtex-5 LXT devices advance the technology even further by including a built-in PCI Express end point engine. This saves FPGA resources for other tasks and offers a standardized internal interface for sending and receiving data.
Figure 4 shows an XMC product for software radio applications that takes maximum advantage of FPGA resources. The Xilinx Virtex-4 SX55 offers a generous 512 DSP slices, highest in the Virtex 4 family, to maximize performance of algorithms critical to software radio like digital downconversion, analysis, energy detection, and demodulation. It also provides interfaces to the many A/D and D/A converters, timing and memory resources.
In addition, the Virtex-4 FX-100 is harnessed for its control and I/O capabilities. A nine-channel DMA controller and a complete PCI interface ensure efficient data transfers to and from the host PCI interface. The RocketIO gigabit serial interfaces are connected directly to the pins of the XMC connection, per VITA 42.0. By installing the appropriate protocol engine inside the FX100, any of the popular serial standards can be supported. Commercial intellectual property (IP) cores for both PCI Express and Serial RapidIO are now available from Xilinx, Altera, and third party sources to save development time.
Architectures like the one in Figure 4 illustrate the central role of FPGAs in PMC and XMC modules, by saving hundreds of discrete devices for improved density and function. The ability to add custom signal processing algorithms, control functions and protocol engines helps broaden the market space and extend product lifecycles. As FPGAs acquire more functions, future XMC offerings will surely benefit, ensuring them a secure and long-lasting role in high-performance embedded systems.
The claim that FPGAs have been the single most important factor in XMC adoption should now be justified. Because of FPGAs, the only incremental hardware cost to the PMC card vendor is adding copper traces from the FPGA gigabit serial interface pins to the pads of the XMC connector. The larger investments in software, drivers and FPGA development can be tuned to the market demands as appropriate. Now that XMC compliant hardware is proliferating, these investments are already being made.
To view GateFlow® FPGA Design Resources, click here.
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